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TiWi-SL MODULE
DATASHEET
DEVICE POWER-UP AND ENABLE
Normal operation mode requirements:
1. The MODE1 and MODE2 signals need to be shorted together.
The normal SPI host write sequence is SPI_CS low (host ? module), followed by SPI_IRQ low (module ? host),
indicating that the device is ready to accept data.
At Power-up, the sequence is slightly different. SPI_IRQ will go low (module ? host) indicating the module has
completed the power up sequence. The Host must wait an additional time (T2) from the assertion of SPI_CS (that
is, bring SPI_CS low) before sending the first SPI packet.
Power-up sequence timing requirements:
1. Apply power to the module through the VCC input.
2. Wait for the module to power-up and stabilize (T0). This is to allow onboard oscillators to stabilize.
3. Enable the module through the PWR_EN input.
4. Wait for SPI_IRQ to be brought low by module (T1) before asserting CS.
5. Wait an additional time (T2) for the module to be ready before sending first packet.
Figure 4 Device Power-Up Timing
Timing Parameter
VCC to PWR_EN Delay
PWR_EN to SPI_IRQ
SPI_IRQ to SPI_CS
Symbol
T0
T1
T2
Max
1000
53
7
Unit
ms
ms
ms
Table 19 Device Power-Up Timing
The information in this document is subject to change without notice.
330-0085-R3.0
Copyright ? 2011-2012 LS Research, LLC
Page 22 of 39
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